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Cypress Semiconductor /psoc63 /PERI /GR[1] /CLOCK_CTL

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Interpret as CLOCK_CTL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0INT8_DIV

Description

Clock control

Fields

INT8_DIV

Specifies a group clock divider (from the peripheral clock ‘clk_peri’ to the group clock ‘clk_group[3/4/5/…15]’). Integer division by (1+INT8_DIV). Allows for integer divisions in the range [1, 256].

Note that this field is retained. However, the counter that is used to implement the division is not and will be initialized by HW to ‘0’ when transitioning from DeepSleep to Active power mode.

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data